1. Field of the Invention
The present invention relates to an integrated circuit and an access control method, and in more specific terms, it relates to an integrated circuit having an access control unit that controls access to an external device and an access control method employed therein.
2. Description of the Related Art
An external device connected to a semiconductor integrated circuit (hereafter referred to as an xe2x80x9cLSIxe2x80x9d) has an access time which is inherent to the particular device. The access time in this context refers to the length of time that elapses until access to the external device is enabled, and the LSI waits for the access time to elapse and then accesses the external device.
Under normal circumstances, an LSI connected to an external device is provided with an access control unit that controls access to the external device by setting a wait (standby) time to elapse until the external device access time is up. This access control unit is provided with a wait cycle number setting register and a wait signal generating circuit that determines the actual number of wait cycles based upon data set at the wait cycle number setting register. It is to be noted that the number of wait cycles corresponds to the number of clocks in a clock signal at the LSI, and the wait time is determined as the product of the number of wait cycles and a clock signal cycle.
The wait signal generating circuit provided in an LSI in the prior art calculates the number of wait cycles xcex1n by using a formula for determining a general term xcex1n in an arithmetic progression:
xcex1n=a+(nxe2x88x921)dxe2x80x83xe2x80x83(formula 1)
In the formula above, n represents a value corresponding to the data set at the wait cycle number setting register, and the explanation, is given here on the assumption that n=1 when the data set at the wait cycle number setting register indicate xe2x80x9c0xe2x80x9d with n increasing by 1 each time the number of sets of data increases by 1.
For instance, when; a (initial term)=1 and d (common difference)=1 in (formula 1) and data indicating xe2x80x9c0xe2x80x9d are set (n=1) at the wait cycle number setting register, as illustrated in FIG. 3, the number of wait cycles xcex1n is determined to be xcex1n=1 by the wait signal generating circuit. Then, as the number of sets of data set at the wait cycle number setting register increases, the number of wait cycles xcex1n is obtained as (2, 3, . . . , 2Wxe2x88x922, 2Wxe2x88x921, 2W). It is to be noted that W indicates the bit width at the wait cycle number setting register.
There are many different types of external devices connected to LSIs and they have become even more diverse in recent years. In addition, a single LSI may be connected with a plurality of external devices with varying access times, including an external device with a short access time and an external device with a long access time. For this reason, LSI need to be capable of supporting varying access times.
However, the number of wait cycles set at the access control unit provided in the LSI in the prior art constitutes an arithmetic progression as explained above and, as a result, it is necessary to allow a large bit width at the wait cycle number setting register to increase the number of wait cycles.
For instance, when the LSI clock frequency is 100 MHz (cycle 10 ns), a plurality of external devices are connected to the LSI and their access times are all within a range of 10 nsxcx9c1 xcexcs, the maximum of 100 levels (10, 20, 30 . . . 980, 990 ns 1 xcexcs) of wait time can be set. However, the wait cycle number setting register is required to have a bit width of 7 bits to support these wait time setting levels. The circuit scale of the LSI is bound to become large to support a larger bit width at the wait cycle number setting register, which, in turn, leads to an increase in the production costs.
An object of the present invention, which has been completed by addressing the problem of the prior art discussed above is to provide an integrated circuit and an access control method, that support external devices with varying access times without having to increase the circuit scale.
In order to achieve the object described above, in a first aspect of the present invention, an integrated circuit having an access control unit that controls access to an external device is provided. The access control unit comprises a register at which n types of data, i.e., a first set of data through an nth set of data, can be set, a wait signal generating circuit that calculates the number of wait cycles axc2x7rkxe2x88x921 (a and k are integers) to output a wait signal over the length of time corresponding to the number of wait cycles axc2x7rkxe2x88x921 calculated when the data set at the register is a kth set of data (1xe2x89xa6kxe2x89xa6n) and an interface unit that is connected with the external device and is forbidden to access the external device while the wait signal is output by the wait signal generating circuit.
Since the wait signal generating circuit calculates the number of wait cycles based upon the data set at the register and the formula for determining a general term in an arithmetic progression, a plurality of wait cycle numbers calculated by the wait signal generating circuit constitute the arithmetic progression. In other words, when the value indicated by the data set at the register increases by one, the number of wait cycles increases exponentially. Thus, even when the register bit width is small, the maximum value for the number of wait cycles that can be set is increased.
In a second aspect of the present invention, the interface unit includes a clock mask circuit and a flip-flop. It is desirable that the clock mask circuit be provided with a first input terminal to which the wait signal is input, a second input terminal to which a clock signal is input and an output terminal that is fixed at a specific logic level when the wait signal is being input to the first input terminal but is engaged to output the clock signal input to the second input terminal when the wait signal is not being input to the first input terminal. In addition, the flip-flop should preferably be capable of taking in external data from the external device in synchronization with a clock signal output via the output terminal of the clock mask circuit.
By adopting this structure, in which the clock mask circuit can be constituted by employing a simple logic gate such as an OR gate, a clock signal to be provided to the flip-flop can be effectively cut off by the wait signal. As a result, since the flip-flop cannot take in the external data output by the external device unless a clock signal is input therein, the wait signal is ultimately used to prohibit/allow access between the integrated circuit and the external device.
In a third aspect of the present invention, a method of controlling access between an integrated circuit and an external device connected to the integrated circuit is provided. This access control method comprises a step in which a kth set of data (1xe2x89xa6k xe2x89xa6n, k is an integer) is set at a register at which n types of data, i.e., a first set of data through an nth set of data can be set, a step in which the number of wait cycles axc2x7rkxe2x88x921 (a is an integer) is calculated, a step in which a wait signal is set in an active state over a length of time corresponding to the number of wait cycles axc2x7rkxe2x88x921 and a step in which access to the external device is prohibited while the wait signal remains in an active state.